Random constraint on "rand bit [255:0] foo"

SystemVerilog
,
1

rand bit [255:0] foo;

There is a control knob called “fie”.

If fie = 0, foo = 256’h0;
If fie = 1, only 1 bit in foo (at a random location) should be 1.
If fie = 2, only 2 bits in foo (at random locations) should be 1.
If fie = 3, only 3 bits in foo (at random locations) should be 1.

How do I write this constraint? Please help. Thank You!

2

constraint fiefoo { $countones(foo) == fie;}

3

In reply to dave_59:

Thank You Dave!