RAL read and write issues to Design

In reply to chr_sue:


class apb_adapter extends uvm_reg_adapter;
     `uvm_object_utils(apb_adapter)

   function new(string name ="apb_adapter");

       super.new(name);
       supports_byte_enable = 0;
       provides_responses = 0;
     
 
  endfunction



  virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
       apbTransaction pkt = apbTransaction::type_id::create("pkt");
      
       

       pkt.Direction = (rw.kind == UVM_WRITE) ? APB_DIRECTION_WRITE :APB_DIRECTION_READ;
       pkt.Addr = rw.addr;
     //pkt.pwdata = (rw.kind == UVM_WRITE)?rw.data:pkt.pwdata;
      // if(rw.kind == UVM_WRITE) begin   
            pkt.Data = rw.data;
     //  else    
         //   pkt.prdata = rw.data;
     //  end


    //  if(rw.kind == UVM_READ) begin 
        //  pkt.Data = rw.data;
    // end 
        `uvm_info(get_type_name(),"ADAPTER...",UVM_NONE)  
 
       `uvm_info(get_type_name(),$sformatf("reg2bus addr=%0h data=%0h",pkt.Addr,pkt.Data),UVM_NONE) 
      return pkt;
   endfunction


  virtual function void bus2reg (uvm_sequence_item bus_item,ref uvm_reg_bus_op rw);


    apbTransaction  pkt;
    


    if(!$cast(pkt,bus_item)) begin 
             `uvm_fatal ("reg2apb_adapter","Failed to cast bus_item to pkt")
    end 

  
   rw.kind = pkt.Direction ==APB_DIRECTION_WRITE ? UVM_WRITE : UVM_READ;
   rw.addr = pkt.Addr;
   rw.data = pkt.Direction ==APB_DIRECTION_WRITE ?pkt.Data:pkt.Data;
   rw.status =UVM_IS_OK;
     `uvm_info ("adapter",$sformatf("bus2reg : addr=0x%0h data=0x%0h kind=%s status=%s",rw.addr,rw.data,rw.kind.name(),rw.status.name()),UVM_DEBUG)
  endfunction
endclass



This is my adapter. Don’t know why bus2reg doesn’t work