In reply to chr_sue:
Forget about the stimulus for a second. I’m driving a valid stimulus to the DUT where a read and a write CAN happen to my DUT at the same time. It’s part of the spec for my DUT. If both happen at the same time, then my DUT is expected to handle both such that it writes the data into the address first and then reads out the memory. There is no issue/question with my stimulus.
Both of your previous suggestions are to drive write and read separately! That’s not what I want. I want to test my DUT when both happen together.
Yes, they can share the addresses between the read port and write port.
I don’t agree to your statement “when you are executing reads and writes with the same clock cycle. This will end up in a bad situation.”
My DUT is intelligent enough to handle reads/writes together. You don’t have to worry about that. Let’s focus on the testbench!
What should I do in my monitor/scoreboard to ensure that my TB also handles these writes/reads together!