In reply to vignesh.kannan:
It’s useless to have delays in generating seq_items. Any timing will be done in the drivers. Your seq_items my have a data member defining the delays between the execution of read or writes.
I believe it is useless to do reads without doing writes prior to the reads. And do you share addresses between the read and the write port?
Back to your last statment: when you are executing reads and writes with the same clock cycle. This will end up in a bad situation. Inserting an additional clock cycle in the read access will delay this and you have a clear situation.