Question regarding check for one feature

SystemVerilog
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1

My question is client will send one request to memory, memory has to send response back to client with in 1000 cycles. I have to write a check in such a way that if memory will take more than 1000 cycles I have to rise timeout flag. My doubt is I need to write an assertion or scoreboard check for this kind of checking. I think in assertions it is comparatively easy if I want to write a check in scoreboard I dont have any idea how to proceed further can any one help for this checker.

2

In reply to marathuteja:
Your question seems to be: How do I write an equivalent concurrent SVA assertion in a scoreboard that is a class. Concurrent assertions are illegal in classes.
I explain this concept in my paper Understanding the SVA Engine Using the Fork-Join Model Verification Horizons Using a model, the paper addresses important concepts about attempts and threads. Emphasizes the total independence of attempts.

I came up with a quickly tested model of your requirements using SVA and a class.
For simplicity, I embedded the class into the module so as to quickly have access to the module variables, and without having to go thru a virtual interface. The latency can be changed to 1000, but for this test, I set it to 5 for simplicity

Edit code - EDA Playground // code
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  /* My question is client will send one request to memory, 
  memory has to send response back to client with in 1000 cycles. 
  I have to write a check in such a way that if memory will take more than 1000 cycles 
  I have to rise timeout flag. 
  My doubt is I need to write an assertion or scoreboard check for this kind of checking. 
  I think in assertions it is comparatively easy 
  if I want to write a check in scoreboard I dont have any idea 
  how to proceed further can any one help for this checker. */
      

  module my_module;
  bit clk, req, rdy, acq_flag;
  int pass, fail, latency=5; // 5 instead of 1000 for this test. 
  class c;
  task scoreb(); 
     forever 
       if (req==1) test(); 
       else @(posedge clk);
  endtask
  task test(); 
     int v=latency; 
     while (v>=0) begin 
       @(posedge clk) v=v-1; 
       if(rdy || v<0) break;
     end
     @(posedge clk) assert((acq_flag==1 && v<0) || (acq_flag==0 && v >=0))
     pass=pass+8; else fail=fail+8; ;
  endtask
endclass
  property p_req_rdy; 
    int v_count; 
    @(posedge clk) ($rose(req), v_count=latency) |=> 
       (1, v_count=v_count-1)[*1:$] ##0 ((v_count < 0) || rdy)
    ## 1 (acq_flag && v_count<0) || (!acq_flag && v_count>=0);
  endproperty
  ap_req_rdy: assert property(p_req_rdy) pass=pass+1; else fail=fail+1;

  c c1=new(); 
  initial c1.scoreb(); 

  initial forever #1 clk = !clk;
  initial begin
     $dumpfile("dump.vcd"); $dumpvars; 
     #2 @(posedge clk) req <= 1; @(posedge clk) req<=0; 
     repeat(2) @(posedge clk); rdy <=1; @(posedge clk) rdy <= 0;
     repeat(2) @(posedge clk); 
     #2 $finish;
  end
endmodule

Ben Cohen
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