Question on fork

SystemVerilog
,
1

Write a timeout detection check to flag an error if “status ok” is not asserted with in 1microsecond of asserting “start”. using fork not with assertion can any one help me how to write a fork block for this check.

2

In reply to marathuteja:

Something like this maybe ?

module test();
  int start = 1;
  int status;
  bit timeout_flag = 0;
  
  initial begin
    
    wait(start==1) ;
    fork begin //isolator
      fork 
        begin
          wait(status == 1) ; //wait for status ok
        end
        begin
          #1us;
          timeout_flag = 1;
        end
      join_any;
      if(timeout_flag == 1) 
        $display("Fail");
      disable fork;  
    end join //isolator
    
  end
  
endmodule
3

In reply to KillSteal:

KillSteal has a good start, but I prefer the approach I used in my paper
**Understanding the SVA Engine Using the Fork-Join Model
** Verification Horizons
Using a model, the paper addresses important concepts about attempts and threads. Emphasizes the total independence of attempts.

Note that for every posedge of start I trigger the automatic task check_ok.
This is just like a concurrent assertion where at every clocking event you trigger the property.

Edit code - EDA Playground // code
EPWave Waveform Viewer // wave
I modified the units of time for demo use.


// Write a timeout detection check to flag an error if "status ok" is not asserted 
// within 1microsecond of asserting "start". using fork not with assertion can any 
// one help me how to write a fork block for this check.

module test();
    typedef enum {IDLE, OK} status_e;  // 
     //status_e status; 
     int status=0;
     bit start, started; 
     int pass, fail; 

  always @(posedge start) 
      fork check_ok(); // trigger the task 
      join_none

    task automatic check_ok();
      bit timeout_flag=0; 
      started=1; // debug
      fork begin 
        fork 
          begin
            // if(status == 0) @(posedge status) pass=1; //wait for status ok
            wait(status==1); // above works too
          end
          begin
            #15;
            timeout_flag = 1;
          end
        join_any;
        am_stat_ok: assert(timeout_flag == 0) pass=pass+1; 
        else begin fail=fail+1; $display("Fail"); end
        //disable fork;  
      end join //isolator
    endtask

    initial begin
        $dumpfile("dump.vcd"); $dumpvars;
        status=0; //IDLE;
        #10 start=1; 
        #3 status=1;
        #30 status=0;
        #3 $finish;    
    end
  endmodule

Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.

or Cohen_Links_to_papers_books - Google Docs

Getting started with verification with SystemVerilog