I’m currently trying to build up a UVM verification environment to understand UVM frame structure and Mentor Questa QVIPs usage as well.
This verification environment will include Questa UART and SPI QVIPs from Mentor.
I’ve a top-level virtual sequencer, which will have both custom developed sequencers for some agents and also Mentor UART / SPI QVIPs agents’ sequencers…
I use Mentor Questa QVIPs , version 10.4c_1 b by the way.
I could not find anywhere in documentation of QVIPs (UART QVIP for instance) how to declare Questa QVIPs sequencers inside a top virtual sequencer…
There’s no share a UART sequencer class sv file anywhere that I can use to declare it inside top-level virtual sequencer…Inside UART QVIP examples, in test.svh file,
I see following lines to run some sequences on the uart device/agent sequencer…But this is not exactly what I need…I need to instantiate UART sequencer inside top-level virtual sequencer…
//Run the source sequence on the processor.
source_seq.start(env.uart_dev_agent.m_sequencer);
I aim to develop a top-level env., which is shown on page 241 of uvm cookbook-complete-verification academy doc./pdf.
There are sub env., in which some has virtual seq., but also there will be some agents with their standalone sequencers (questa QVIPs for example)…
But I need to control all from a top-level virtual sequencer, hence I have to declare QVIPs sequencers in top-level virtual sequencer and connect them inside top-env class file…
Can you please help me on this issue so that I can progress on learning Mentor Questa QVIPs usage and UVM env.?
Riza