Query on polymorphism

SystemVerilog
,
1 

module tb;

class base;

virtual function void base_f;
  $display("base_f from Base Class");
  base_f2;
endfunction

function void base_f2;
  $display("base_f2 from Base Class");
endfunction

endclass

class extension extends base;

function void base_f;
  $display("base_f from Extended Class");
  base_f2;
endfunction

function void base_f2;
  $display("base_f2 from Extended Class");
endfunction

endclass

initial begin
  base b;
  extension e;
  e = new();
  b = e;
  b.base_f();
end

endmodule

Output -
base_f from Extended Class
base_f2 from Extended Class

Here only base_f is declared virtual. base_f2 which is called inside base_f is non-virtual. By looking at the output, it looks like we don’t have to declare the sub-function as virtual.
Out of curiosity, is there any specific reason behind this behavior? Does LRM mention about this anywhere?

2

In reply to naveensv:

When declaring a virtual method, you cannot change any aspect of its prototype in any extension—including the virtual qualifier.

Virtual method overrides in subclasses shall have matching argument types, identical argument names, identical qualifiers, and identical directions to the prototype. The virtual qualifier is optional in the derived class method declarations.