Push the starting edge of the input clock 520 ns out from the output clock

SystemVerilog
,
1

Hi,

i want to push the starting edge of the input clock 520 ns out from the output clock. Can anyone let me know how it can be done.

I tried this but not working

assign #500ns sf0_spihb_clk_in_delay =  sf_sf0_spihb_clk_in;
assign #500ns sf1_spihb_clk_in_delay =  sf_sf1_spihb_clk_in;


sf_sf*_spihb_clk_in is wire coming from another module.

Thanks,
Tejas
2

In reply to tejasakulu:
Should work, below does;


/* i want to push the starting edge of the input clock 520 ns out from the output clock.
 Can anyone let me know how it can be done.
assign #500ns sf0_spihb_clk_in_delay =  sf_sf0_spihb_clk_in;
assign #500ns sf1_spihb_clk_in_delay =  sf_sf1_spihb_clk_in; 
sf_sf*_spihb_clk_in is wire coming from another module. */
module top;
    timeunit 1ns;  timeprecision 100ps;   
    bit  clk_out, clk_in;
    wire ckw_in, ckw_out; 
    assign ckw_in=clk_in; 
    assign #500ns ckw_out = ckw_in;

    initial forever #700 clk_in = !clk_in;
    always @(clk_in) begin
        if(clk_in) #500 clk_out=1'b1; 
        if(!clk_in) #50 clk_out=1'b0; // could change to 500
    end
  
    initial begin
        clk_in=1'b0;
      repeat (20) begin
        @(posedge clk_in);
      end
      $finish;
    end
  endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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