Push_pull, open drain in verilog

UVM
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2

In reply to Dhee_27:

Here’s a good explanation about the concepts.

Push/Pull is the normal mode of most gate outputs - drive a zero or one. Open-drain can drive a zero or high-Z. In Verilog, this can be done with a continuous assignment.

assign push_pull = data_reg;     // implicit
assign (strong0, strong1) push_pull = data_reg; // explicit 
assign (strong0, highz1) open_drain = data_reg;

If this needs to be programmable, you can use a mode bit.

assign bus = mode ? push_pull : open_drain;
assign (pull1,highz0) = 1; // pull-up