Pullup in sv

SystemVerilog
1

hi.
i wanted to have the pull up functinality in sv.
how to implement same, kindly guide.

Regards,

2

I’m assuming you are talking about a signal in an interface since your other question is about modports.

Just declare the signal as a ‘tri1’ nettype, or use a continuous assignment with a pull strength.

tri1 *signal*;
or
wire *signal*;
assign (pull1,pull0) *signal* = '1;

Then treat the signal as you would any other bi-directional and drive it with a 'z when you want the pullup to have an effect.

3

In reply to dave_59:

Hi Dave,

Please help me.
Can you explain about it?
pullup(dp);
If I use this method to pullup pin dp.
I read the SystemVerilog Document but it is complicated.
I can’t understand clearly.
And another question:
what do you think if I replace command pullup(dp) by the commands below?
reg dp;
initial begin
dp = 1;
repeat(5) @(posedge clk);
dp = 0;
end

Thank you
Kaitoo

4

In reply to KaitooKid:

And I don’t know but I use your method it’s not work.

5

Probably you need to understand strength modelling.
Below link might help you.

6

In reply to kiru2006:

Thanks