Pullup in sv

SystemVerilog
2

I’m assuming you are talking about a signal in an interface since your other question is about modports.

Just declare the signal as a ‘tri1’ nettype, or use a continuous assignment with a pull strength.

tri1 *signal*;
or
wire *signal*;
assign (pull1,pull0) *signal* = '1;

Then treat the signal as you would any other bi-directional and drive it with a 'z when you want the pullup to have an effect.