In reply to m_v:
See sections 4.6 Determinism, 4.7 Nondeterminism, and 4.8 Race conditions in the IEEE 1800-2017 SystemVerilog LRM
In reply to m_v:
See sections 4.6 Determinism, 4.7 Nondeterminism, and 4.8 Race conditions in the IEEE 1800-2017 SystemVerilog LRM