Problem with fork join_any and disable fork

SystemVerilog
, ,
1

hello, can anyone check why i am getting this type of output while using fork join_any?

code:-


module test;
  int a;
  initial begin
    fork
      begin
        $display($realtime,,,,,,"before disable");
      end
      
      begin 
        repeat(10) begin
          $display($realtime,,,,,,"a = %0d",a++);
        end
      end      
    join_any 
    disable fork;
    $display($realtime,,,,,,"after disable");
  end
endmodule

Actual output from questasim:-

0 before disable

0 a = 0

0 a = 1

0 a = 2

0 a = 3

0 a = 4

0 a = 5

0 a = 6

0 a = 7

0 a = 8

0 a = 9

0 after disable

expected output :
0 before disable
0 after disable

You can also run the code:- Edit code - EDA Playground

Thank you.

2

Both the threads with in the fork join block doesn’t consume any delay, both of them will be completed at 0 time unit only.

3

In reply to shanthi:

I also ran this code with VCS it was giving output as expected can you explain why?

4

In reply to shanthi:
But many processes run at zero simulation time, that differentiation has to be done by the tool.
Ex -
fork
thread1 display1
thread2 display2
thread3 display3
join

multiple process in fork join at zero simulation time, but still tool executes them one by one.
output will be: -
display1
display2
display3

5

In reply to m_v:

This is a race condition. The only guaranteed output is that if printed, “a=0…a=9” must be in order, and that the "after disable must be the last output line. So technically the following is another valid output

0 a = 0

0 a = 1

0 a = 2

0 a = 3

0 before disable

0 a = 4

0 a = 5

0 a = 6

0 after disable

6

In reply to dave_59:

hi Dave, In this all the display statements will be executed in active region and at 0 time so the order of the display is as the user’s order of the display statements so why the #0 before disable is in between and now as per your output the #0 before disable can be any where but before the #0 after disable right?

7

In reply to m_v:

See sections 4.6 Determinism, 4.7 Nondeterminism, and 4.8 Race conditions in the IEEE 1800-2017 SystemVerilog LRM

8

In reply to m_v:

module test;
int a;
initial begin
fork
begin
$display($realtime,“before disable”);
end
/*
begin
repeat(10)begin
$display($realtime,“a = %0d”,a++);
end
end
*/

  begin
   $display($realtime,,,,,,"after disable");
    end
 join_any
/*
 disable fork;
   $display($realtime,,,,,,"after disable");

*/
end
endmodule

with this code, you can get the expected output