PROBLEM IN INITIALIZATION IN TCAM MEMORY

UVM
, ,
1

I have a DUT memory (reg [7:0]mem[255:0] ) , having a problem in initializing the values with own address( addr 0 → val 0, addr 1 → val 1…addr 255 → val 255)

/// SET SEQUENCE BODY METHOD
virtual task body();

		tcam_transaction set_tx;
		 set_tx = tcam_transaction::type_id::create("set_tx");
    for(int i=0; i<256 ;i++) begin 
		 start_item(set_tx);
      
                 assert( set_tx.randomize()  with {  set_tx.set_valid == 1;   set_tx.set_addr == i ; set_tx.set_key == i ;  }    ); 
		
		  finish_item(set_tx);
        end 

	endtask
endclass : set_tcam_sequence

//////drivers run phase

virtual	task run_phase(uvm_phase phase );
  	tcam_transaction  tx;  
		forever begin 
          @(vif.driver_cb) ;
	    
		seq_item_port.get_next_item(tx);
       
          @(vif.driver_cb);
          
         if( vif.driver_mp.rst == 1'b1 ) 
             begin 
              	 vif.driver_cb.set_addr  <=  0;
				 vif.driver_cb.set_valid <=  0;
				 vif.driver_cb.set_key   <=  0;
				 vif.driver_cb.set_xmask <=  0 ;
	    		 vif.driver_cb.req_key   <=  0 ;
         		 vif.driver_cb.req_valid <=  0 ;
            
          end 
             
          else 
                  begin   
               
			    vif.driver_cb.set_addr  <=  tx. set_addr;
			    vif.driver_cb.set_valid <=  tx. set_valid;
		 		vif.driver_cb.set_key   <=  tx.set_key;
			    vif.driver_cb.set_xmask <=  tx. set_xmask;
	   		    vif.driver_cb.req_key   <=  tx. req_key;
                vif.driver_cb.req_valid <=  tx.req_valid;
                    
                   end
		 seq_item_port.item_done();
		end
    endtask

 endclass : tcam_driver

problem arises in dut initialization
mem[0]= 0
mem[0]= 0
mem[1]= 0
mem[1]= 1
mem[2]= 0
mem[2]= 2
mem[3]= 0
mem[3]= 3
mem[4]= 0
mem[4]= 4
…
…
…
mem[254]= 0
mem[254]= 254
mem[255]= 0
mem[255]= 255

// why the values 0 is written at very location

when i am checking in subscriber/////////////////////////////////////////////////////////////////////// EXPECTED line_match 74
UVM_INFO testbench.sv(478) @ 5155000: uvm_test_top.tcam_env_h.tcam_sub [SCORE BOARD] req_valid = 1 req_key = 74 linematch = 0 ///due to wrong /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////initialization
UVM_FATAL testbench.sv(497) @ 5155000: uvm_test_top.tcam_env_h.tcam_sub [tcam_subscriber] Faillllllll

2

In reply to dhanunjay:

Declare your memory like this:

memory reg [7:0]mem[0:255];
3

In reply to chr_sue:

problem persists

4

In reply to dhanunjay:

How do you control the reset signal?
Is there a time progress between the values?.

5

In reply to chr_sue:

I’m a using a EDA playground and i’m new to UVM coding
//in module top_test;
initial begin
rst = 1’b1;
#20 ;
rst = 1’b0;
end

and passing the rst to interface block
& module
Set/Clear latency: 1
Request latency: 3

6

In reply to dhanunjay:

Could you please provide the link to EDAPlayground?

7

In reply to chr_sue:

8

In reply to dhanunjay:

Thanks.
I had a look and I can see you are initialising your design twice, once in the design itself youa re setting the memory content to 0 and secondly you are doing this from your testbench.
This results in the data you can see here: