PROBLEM IN INITIALIZATION IN TCAM MEMORY

In reply to chr_sue:

I’m a using a EDA playground and i’m new to UVM coding
//in module top_test;
initial begin
rst = 1’b1;
#20 ;
rst = 1’b0;
end

and passing the rst to interface block
& module
Set/Clear latency: 1
Request latency: 3