Printing value of a local variable within a property

SystemVerilog
1

Hi

I am trying to print the value of a design signal when the antecedent gets fired of a given assertion:

For e.g

property read_check
logic [7:0] read_addr
@(posedge clk)
(mem_enable && read_enable,read_addr = ) → ##4 $rose(ready)
end proprty

I want to capture and print the value of the read address when the antecedent gets fired and print it when the consequent is evaluated. I tried to do the below but it doesn’t recognize the local variables within a property. I seem to be able to use the variable within the property but is there a way I can print it to a log?

assert property (read_check) begin
$info(“Read address is”,read_addr)
end

2

Local variables are not visible outside the property.

you can add a display statement like this…

property read_check
logic [7:0] read_addr
@(posedge clk)
(mem_enable && read_enable,read_addr = rdata, $display(“read_addr=0x%0x”,read_addr)) |-> ##4 $rose(ready)
end proprty

3

In reply to pavan yala:

Tried the above. It now says its an illegal use of the system task ‘$display’ as a function.

Was also thinking about using $past to print out the antecedent signal but the consequent could fire after different number of clock cycles each time and not sure if I would be able to get the exact value to pass as an input to $past

4

In reply to tabhay85:

You cant use a local variable in assert statement. You can use $display as shown

property read_check;
logic [7:0] read_addr;
@(posedge clk)
(mem_enable && read_enable,read_addr = rdata, $display("read_addr=0x%0x",read_addr)) |-> ##4 $rose(ready);
endproperty

This should work.
Please check your syntax errors properly like semicolons, bracket opening and closures. If still your getting errors, Just post it what are the errors and code.

5

In reply to Anudeep J:
You could also use a function call that may even have side effects, though side effects are generally not recommended. For example:


   int count=0; 
   function logic[7:0] do_something(logic [7:0] read_addr);
      $display("read_addr=0x%0x",read_addr);
      count=count+1'b1; // <-- A side effect !!!
    endfunction : do_something
 
   property read_check;
     logic [7:0] read_addr;
     @(posedge clk)
        (mem_enable && read_enable,read_addr = rdata, do_something(read_addr)) 
                   |-> ##4 $rose(ready);
   endproperty

    assert property (read_check);

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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6

In reply to ben@SystemVerilog.us:

Yes Ben, Function call is also possible.