Printing value of a local variable within a property

SystemVerilog
4

In reply to tabhay85:

You cant use a local variable in assert statement. You can use $display as shown

property read_check;
logic [7:0] read_addr;
@(posedge clk)
(mem_enable && read_enable,read_addr = rdata, $display("read_addr=0x%0x",read_addr)) |-> ##4 $rose(ready);
endproperty

This should work.
Please check your syntax errors properly like semicolons, bracket opening and closures. If still your getting errors, Just post it what are the errors and code.