Post implementation timing simulation error

SystemVerilog
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1

I generated the netlist and sdf file for my design on Vivado, compiled the necessary libraries and ran post implementation timing simulation on questasim. However an error during sdf back annotation appears:

Error (suppressible): (vsim-SDF-12088) Failed to find matching specify module path for IOPATH. [DSP_M_DATA(fast): DSP_M_DATA.v(29)] Instance:‘…/DSP_M_DATA_INST’ : from ‘V’ : to ‘V_DATA’.

Do you know the solution for this ?

2

In reply to Farah_Adel_Fathy:

Impossible to answer your question without knowing if you think that path:

  1. exists in your design, then showing the code to support it
  2. does not exist and then why Vivado might have generated that path

You might also have to show the commands used to annotate the SDF.

Unfortunately this might run into tool specific behavior. This Mentor/Siemens EDA sponsored public forum is not for discussing tool specific usage or issues. Please read your tool’s user manual or contact your tool vendor directly for support.