Performance impact of @

SystemVerilog
,
1

What could be the performance difference with below two ways? or is there any?

@(posedge clk);
@(posedge clk iff enable_1 && enable_2);

Wanted to know which is the better way wherever possible?

Thank you,
Mega

2

In reply to megamind:
I don’t believe that there is a performance difference.
I prefer the simpler construct


always @(posedge clk)
if (enable) ...

Ben

3

In reply to megamind:

This kind of question requires more context. The two statements you wrote are not behaviorally equivalent. And if you meant to compare the iff construct with the if statement that Ben wrote, we would really need to know the percentage of activity the iff condition was true in relation to the number of clock edges.

In any case, you should spend time learning your tool’s performance profiler so know you to focus on issues having a better chance of improving performance.

4

In reply to dave_59:

Thank you Dave and Ben.