Passing value to macro

SystemVerilog
1

HI All,

I have defined a macro like below

`define form_name(arg) f_def_start_``arg

i wanted to pass value to the macro like below (defined inside a class)

string act_field_val;

for(int i=0; i<3; i++) begin
    act_field_val = `form_name(i);
end

however the result is “f_def_start_i” instead of “f_def_start_0, f_def_start_1, f_def_start_2”.
could anyone help.
Thanks

2

In reply to Vdas:
https://verificationacademy.com/forums/systemverilog/2-variable-macro-definition-path-instance-inside-loop-not-working#reply-90856

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