2 variable macro definition for path instance inside for loop not working

SystemVerilog
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1

I have a some hierarchical instances of registers that I ultimately want to pass into a $display and print out the value of the register at the instance location.

I have a macro defined as:

`define WriteDataOut(j,i) dut_foo.I``j``.I``i``.I0.DATA_OUT

where j loops from 11-19, i loops from 5-8

If for example I print out a single hard path I get my DATA_OUT value as expected.


$display("%0t DATA_OUT value is:       0x%0h", $time,  dut_foo.I11.I5.I0.I1.DATA_OUT) ;

DATA_OUT value is: 0x3906c

If I try using a loop to print out all he paths it never inserts the value of i and j into the path and instead gives me this:

(vopt-7063) Failed to find ‘Ijj’ in hierarchical name ‘dut_foo.Ijj.Iii.I0.DATA_OUT’.

my code:

 for (int j=11; j<=19; j++) begin
         automatic int jj = j;  	   
	 for (int i=5; i<=8; i++) begin  		  
	    automatic int ii = i; 	           	  		  
            begin
	       //attempt to print out both the path and value of DATA_OUT for that particular instance. 			
               $display("\dut_foo.I%0d.I%0d.I0.DATA_OUT  	 	 value = 0x%0h", jj,ii, `WriteDataOut(jj,ii));				   
	    end    //begin  
	 end // for (int i=5; i<=8; i++)            
      end // for (int j=11; j<=19; j++)

What I would like it to print out is the following in each line, containing the path and its value. Currently all register instances are identical but they won’t be in the future.

dut_foo.I11.I5.I0.DATA_OUT = 0x3906c;

dut_foo.I11.I6.I0.DATA_OUT = 0x3906c;

dut_foo.I11.I7.I0.DATA_OUT = 0x3906c;

dut_foo.I11.I8.I0.DATA_OUT = 0x3906c;

dut_foo.I12.I5.I0.DATA_OUT = 0x3906c;

dut_foo.I12.I6.I0.DATA_OUT = 0x3906c;

dut_foo.I12.I7.I0.DATA_OUT = 0x3906c;

dut_foo.I12.I8.I0.DATA_OUT = 0x3906c;

dut_foo.I13.I5.I0.DATA_OUT = 0x3906c;

dut_foo.I13.I6.I0.DATA_OUT = 0x3906c;

dut_foo.I13.I7.I0.DATA_OUT = 0x3906c;

dut_foo.I13.I8.I0.DATA_OUT = 0x3906c;.

.
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2

In reply to amveng:
You must remember that macros are pre-processor compiler directives that substitute text for their arguments before any SystemVerilog syntax gets parsed.

Doing what you want in procedural code requires formatting a string and using introspection to look up an identifier by a string name. Only the VPI or a tool specific command can do that.

3

In reply to dave_59:

In a previous post you said “There is no way within the SystemVerilog language to look up variable identifier names by using a string”.

Are you able to give a Questa specific example since you’re from Mentor?

Is there an alternate way I can do what I am looking for?

Thirdly, if I understand the solution you suggested well enough to implement it, will that also print out the value of the register located at the instance location?