Passing real type as input port for module

SystemVerilog
1

I have real variable as input to a module and in the instantiation of the module, I have the connected the real variable itself.
But still I don’t see the effect of it, when I try to display the same in module.
I know in verilog we can’t pass real type as ports ,but in system verilog we can pass.
I am not sure why this is not working.

2

In reply to yaswanth021:
It would really help if you put in some effort to show what you have tried, what results you are getting, versus what you expected to see. This tiny example works for me.

module myModule (input real p);
   always @p $display($time,, p);
   endmodule
module test();
   real r;
   myModule m(r);
   initial begin
      #1 r = 1.2;
      #2 r = 3.4;
      #3 r = 5.6;
      end
endmodule

and produces

#                    1 1.2
#                    3 3.4
#                    6 5.6
3

In reply to dave_59:

module chk(input real val,input en)
real inv_val;
initial
begin
wait(en)
$display("val is %t",val);
end
endmodule

module abc()
real abc_val;
chk chk_inst(.val(abc_val),.en(en))
initial begin
#20ns;
abc_val=130.0;
en=1;
end
endmodule

I see the output of val is 0.000ns

4

In reply to yaswanth021:
OK, that is a little more effort. But you could have posted an example with no syntax errors. This code also worked for me.

module chk(input real val,input en);
//real inv_val; // you did not reference
initial
  begin
     wait(en)
       $display("val is %5.2f",val); // you used %t
  end
endmodule

module abc();  
real abc_val;
   bit en; // did not declare  
   chk chk_inst(.val(abc_val),.en(en));
   
   initial begin
      #20ns;
      abc_val=130.0;
      en=1;
   end
endmodule

Because you used %t, your value gets scaled based on the current $timeformat specification and the default timescale your code was compiled with.

5

In reply to dave_59:

if want to drive testcases and want to keep the port signals , how we can do it?
Actually I wanted to connect DUT and test bench using schematic for that I need port signals of Testbench also

6

In reply to Kiran_amin:

I do not understand your question or how it relates to the thread here. You need to provide more details.

7

In reply to dave_59:

I have a ADC which takes analog input, to test this DUT I want to write testcase which provides real number inputs to the DUT.
I am connecting dut and TEST using schematic, so I have to keep the port level signals in my test also. So my input of adc becomes output port of my test.

Now how can I drive this real value to the DUT using test output port which shoulf be real data type?

module ADC(input vinp,…,vclk, output vout);
end module
//Here vinp is electrical

module test(output vinp,…,vclk,input vout);
output real vinp;
endmodule

8

In reply to Kiran_amin:
It looks like you’re trying to go between SystemVerilog and Verilog-A. You will need to contact your tool vendor for inter-language interoperability.