Passing real type as input port for module

SystemVerilog
4

In reply to yaswanth021:
OK, that is a little more effort. But you could have posted an example with no syntax errors. This code also worked for me.

module chk(input real val,input en);
//real inv_val; // you did not reference
initial
  begin
     wait(en)
       $display("val is %5.2f",val); // you used %t
  end
endmodule

module abc();  
real abc_val;
   bit en; // did not declare  
   chk chk_inst(.val(abc_val),.en(en));
   
   initial begin
      #20ns;
      abc_val=130.0;
      en=1;
   end
endmodule

Because you used %t, your value gets scaled based on the current $timeformat specification and the default timescale your code was compiled with.