Passing array to a task by reference

SystemVerilog
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1

Hi all,

I have a couple of questions about passing array by reference to a task

1 - i have a task with the following prototype
task my_task (ref [31:0] array);
endtask

in my testcase, i have the following variable static logic [31:0] testcase_array[5];

and i call the task : my_task(testcase_array);

i have the following error : ref formal and actual do not have equivalent data types (expecting datatype compatible with ‘dynamic array of packed array [31:0] of logic’ but found ‘unpacked array of packed array [31:0] of logic’ instead).

Is not it valid to pass fixed size array to dynamic array argument ?

2 - The second question : When passing array with reference, each element is considered to be passed by reference ?

Thank you,

2

In reply to aehsan:

The type compatibility rules for an argument passed by reference is very strict. This is because any operation performed on the argument inside the routine is effectively being operated on the argument passed to the routine. You rarely need to pass an argument by reference unless you are calling a time-consuming task and need to have the argument updated while the task is blocked.

For your second question, arrays are aggregate data types and treated like a single object. So the entire array is passed as a single reference.

3

In reply to dave_59:

Thank you Dave,

I did that because i wanted a variable in the test case to follow value of a wire in the design

so i did the following,

  • in the test case i forced the variable to the value of the wire
    static logic [31:0] my_variable;
    force my_variable = wire (path to the wire);
  • my_task use the value of the wire to do some manipulation
    my_task (my_variable); —> This line is called in the test case
  • The task body is as follows:
    task my_task (ref [31:0] my_variable);
    endtask

Notes:

  • Wire is internal signal in the chip
  • The task is implemented for re-usability. The manipulation is repeated for several blocks in the chip
  • For each block, i need to pass several wires, so i used array

Is there another solution to do so ?

4

In reply to aehsan:

You can’t pass a wire by reference, only variables.

A better solution is to use the bind construct to bind a module with a port connected to the wire. That module can have a task inside it that directly references the port.

See my DVCon paper The Missing Link: The Testbench to DUT Connection for an example