In reply to dave_59:
Thank you Dave,
I did that because i wanted a variable in the test case to follow value of a wire in the design
so i did the following,
- in the test case i forced the variable to the value of the wire
static logic [31:0] my_variable;
force my_variable = wire (path to the wire); - my_task use the value of the wire to do some manipulation
my_task (my_variable); —> This line is called in the test case - The task body is as follows:
task my_task (ref [31:0] my_variable);
endtask
Notes:
- Wire is internal signal in the chip
- The task is implemented for re-usability. The manipulation is repeated for several blocks in the chip
- For each block, i need to pass several wires, so i used array
Is there another solution to do so ?