In reply to ben@SystemVerilog.us:
Thank you ben for your answer but I tried it and it works well.
Firstly, I use edaplaygorund and Mentor Questa 2020.1, it works fine.
Secondly, I tried seperately whether inferring clock and reset work or not, it works, I share the code: SVA35 - Concurrent Assertions - 33 - Checker_2 - EDA Playground
You will see it infers clock and reset from the block where it belongs to.
//==================================================================
// Checker Block
//==================================================================
//clock için başta event tanımı kullanıldı, bir tip. Olmasa da doğru çalışyıor.
//reset için ise event çalışmıyor, untyped ya da logic yazılmalı.
//checker checker_1 (clock_delay,a,b, event clk = $inferred_clock, /*reg veya logic*/ untyped reset = $inferred_disable);
//input logic şeklinde daha açık girişler verilebilir.
checker checker_1 (input logic clock_delay, input logic a, input logic b, event clk = $inferred_clock, /*reg veya logic*/ untyped reset = $inferred_disable);
//=================================================
// Shows range usage of $ delay operator
//=================================================
sequence req_gnt_3to5clock_seq;
//req[1] ##[3:$] gnt[1];
a ##[clock_delay:$] b;
endsequence
//=================================================
// Declare property for each of sequence
// We may use more then one seuqnce in a property
//=================================================
property req_gnt_3to5clock_prop;
@ (posedge clk)
disable iff (reset)
//req[1] |-> req_gnt_3to5clock_seq;
a |-> req_gnt_3to5clock_seq;
endproperty
//=================================================
// Assertion Directive Layer
//=================================================
req_gnt_3to5clock_assert : assert property (req_gnt_3to5clock_prop)
$display("** Time : [%0t] - req_gnt_3to5clock_prop PASSED --------", $stime);
endchecker
//==================================================================
// Checker Block
//==================================================================
//+++++++++++++++++++++++++++++++++++++++++++++++++
// DUT With assertions
//+++++++++++++++++++++++++++++++++++++++++++++++++
module hash_sequence();
logic clk = 0;
always #1 clk ++;
logic [2:0] req,gnt;
logic reset=0;
//default clocking ve disable iff yapılıyor, checker bunlardan clock ve reset'i çekiyor.
default clocking @ (posedge clk); endclocking
default disable iff reset;
//=================================================
// Drive the input vectors to test assetion
//=================================================
initial begin
// Init all the values
reset <= 0;
for (int i = 0; i < 3; i++) begin
req[i] <= 0;
gnt[i] <= 0;
end
@ (posedge clk);
req[0] <= 1;
@ (posedge clk);
gnt[0] <= 1;
req[0] <= 0;
@ (posedge clk);
gnt[0] <= 0;
req[1] <= 1;
@ (posedge clk);
req[1] <= 0;
repeat(3) @ (posedge clk);
gnt[1] <= 1;
@ (posedge clk);
gnt[1] <= 0;
req[2] <= 1;
gnt[2] <= 1;
@ (posedge clk);
req[2] <= 0;
gnt[2] <= 0;
// Cause assertion to fail
@ (posedge clk);
req[0] <= 1;
repeat(2) @ (posedge clk);
gnt[0] <= 1;
req[0] <= 0;
#30 $finish;
end
//initialize checker check_1
checker_1 c1 (3, req[1] ,gnt[1]);
initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule