Parameterized Designs

SystemVerilog
1

Hi all,

I have a quick question regarding parameterized designs. In my testbench I am initializing a DUT that requires a parameter called BIT_WIDTH. Is there any way to initialize the DUT’s BIT_WIDTH using a command line argument?

For example, is the following possible?

vcs … +COMMAND_LINE_BIT_WIDTH=10…

module top
Design #(.BIT_WIDTH(COMMAND_LINE_BIT_WIDTH)) dut (…);
…

Thanks,
Billy

2

In Questa the answer is to use a -g switch, this allows you to set the value of Verilog parameters whilst the design is elaborated. Using a command line plusarg requires you to run some code to retrieve the value of the plusarg, this will be after the design has been elaborated - i.e. too late.

To do what you need to do:

module #(int COMMAND_LINE_BIT_WIDTH = 8) top; // Setting 8 as the default value

design #(.BIT_WIDTH(COMMAND_LINE_BIT_WIDTH)) dut (…);

Then in Questa:

vsim top -gCOMMAND_LINE_BIT_WIDTH=10 …

3

In reply to mperyer:

Thanks for reply!

Your suggestion is exactly what I am looking for! After some digging I believe the “-g” counterpart for vcs is “-pvalue”. However, is there a way I can do this if the parameters are defined in a package?

For example,

package some_pkg;
parameter COMMAND_LINE_BIT_WIDTH = 1;
…

import some_pkg::*
module top
design #(.BIT_WIDTH(COMMAND_LINE_BIT_WIDTH)) dut (…);

thanks