In Questa the answer is to use a -g switch, this allows you to set the value of Verilog parameters whilst the design is elaborated. Using a command line plusarg requires you to run some code to retrieve the value of the plusarg, this will be after the design has been elaborated - i.e. too late.
To do what you need to do:
module #(int COMMAND_LINE_BIT_WIDTH = 8) top; // Setting 8 as the default value
design #(.BIT_WIDTH(COMMAND_LINE_BIT_WIDTH)) dut (…);
Then in Questa:
vsim top -gCOMMAND_LINE_BIT_WIDTH=10 …