Plz Ignore the previous wrong code sent by me,
// Code your testbench here
// or browse Examples
module disable_fork;
initial begin
$display("-----------------------------------------------------------------");
//-------------------
//fork-1
//-------------------
fork:MAIN
fork
//-------------------
//Process-1
//-------------------
begin
$display($time,"\tProcess-1 of fork-1 Started");
#5;
$display($time,"\tProcess-1 of fork-1 Finished");
end
//-------------------
//Process-2
//-------------------
begin
$display($time,"\tProcess-2 of fork-1 Started");
#20;
$display($time,"\tProcess-2 of fork-1 Finished");
end
join
//-------------------
//fork-2
//-------------------
fork
//-------------------
//Process-1
//-------------------
begin
$display($time,"\tProcess-1 of fork-2 Started");
#10;
$display($time,"\tProcess-1 of fork-2 Finished");
end
//-------------------
//Process-2
//-------------------
begin
$display($time,"\tProcess-2 of fork-2 Started");
#30;
$display($time,"\tProcess-2 of fork-2 Finished");
end
begin
#22;
$display($time,"\tAfter disable-fork");
disable MAIN;
end
join
join_none
end
endmodule
Plz observe the Simulation results difference b/w the IES, VCS and Aldec Tool.
Query is below the results
SIMULATION RESULTS:
- Cadence IES
irun: 15.20-s038: (c) Copyright 1995-2017 Cadence Design Systems, Inc.
$CDSROOT = /incisiv/15.20
$TESTDIR = /home/runner
TOOL: ncsc 15.20-s038
ncsc C++ parameters:
ncsc -COMPILER $CDSROOT/tools/cdsgcc/gcc/4.8/bin/g++
-f ./INCA_libs/irun.lnx86.15.20.nc/ncsc_run/ncsc_obj/ncsc.args
-MANUAL
-CFLAGS "-DNCSC
-I$CDSROOT/tools/systemc/include_pch
-I$CDSROOT/tools/tbsc/include
-I$CDSROOT/tools/vic/include
-I$CDSROOT/tools/methodology/OVM/CDNS-2.1.2/sc/src
-I/playground_lib/uvm-1.1d/sc/sc
-I/playground_lib/uvm-1.1d/ml/sc
-I$CDSROOT/tools/systemc/include/cci
-I$CDSROOT/tools/systemc/include/factory
-I$CDSROOT/tools/systemc/include/tlm2
-c
-x c++ -m32 -Wall
-I$CDSROOT/tools/include
-I$CDSROOT/tools/inca/include"
ncsc: compiling $/playground_lib/uvm-1.1d/src/dpi/uvm_dpi.cc
$CDSROOT/tools/include/svdpi_compatibility.h:48:2: warning: #warning "INCISIV is currently compliant with DPI header file svdpi.h as per IEEE 1800-2005. Starting IUS16.10, the default header file will be as per IEEE 1800-2012. DPI applications which need to continue complying with IEEE 1800-2005 will need to compile with the macro DPI_COMPATIBILITY_VERSION_1800v2005 starting in 16.1. The difference in the two header files is in the declaration of the struct t_vpi_vecval." [-Wcpp]
#warning "INCISIV is currently compliant with DPI header file svdpi.h as per IEEE 1800-2005. Starting IUS16.10, the default header file will be as per IEEE 1800-2012. DPI applications which need to continue complying with IEEE 1800-2005 will need to compile with the macro DPI_COMPATIBILITY_VERSION_1800v2005 starting in 16.1. The difference in the two header files is in the declaration of the struct t_vpi_vecval."
building library run.so
Top level design units:
disable_fork
ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
Loading snapshot worklib.disable_fork:sv .................... Done
ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
ncsim> source /incisiv/15.20/tools/inca/files/ncsimrc
ncsim> run
-----------------------------------------------------------------
0 Process-1 of fork-1 Started
0 Process-2 of fork-1 Started
0 Process-1 of fork-2 Started
0 Process-2 of fork-2 Started
5 Process-1 of fork-1 Finished
10 Process-1 of fork-2 Finished
20 Process-2 of fork-1 Finished
22 After disable-fork
30 Process-2 of fork-2 Finished
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit
Done
- Synopsys VCS
UVM-1.1d.Synopsys
(C) 2007-2013 Mentor Graphics Corporation
(C) 2007-2013 Cadence Design Systems, Inc.
(C) 2006-2013 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
----------------------------------------------------------------
*********** IMPORTANT RELEASE NOTES ************
You are using a version of the UVM library that has been compiled
with `UVM_NO_DEPRECATED undefined.
See http://www.eda.org/svdb/view.php?id=3313 for more details.
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.
(Specify +UVM_NO_RELNOTES to turn off this notice)
-----------------------------------------------------------------
0 Process-1 of fork-1 Started
0 Process-2 of fork-1 Started
0 Process-1 of fork-2 Started
0 Process-2 of fork-2 Started
5 Process-1 of fork-1 Finished
10 Process-1 of fork-2 Finished
20 Process-2 of fork-1 Finished
22 After disable-fork
V C S S i m u l a t i o n R e p o r t
Time: 22 ns
CPU Time: 0.260 seconds; Data structure size: 0.1Mb
Wed Jul 24 09:11:25 2019
Done
- Aldec Simulation
VSIMSA: Configuration file changed: `/home/runner/library.cfg'
ALIB: Library `work' attached.
work = /home/runner/work/work.lib
MESSAGE "Pass 1. Scanning modules hierarchy."
MESSAGE "Pass 2. Processing instantiations."
MESSAGE "Pass 3. Processing behavioral statements."
MESSAGE "Running Optimizer."
MESSAGE "ELB/DAG code generating."
MESSAGE "Unit top modules: disable_fork."
MESSAGE "$root top modules: disable_fork."
SUCCESS "Compile success 0 Errors 0 Warnings Analysis time: 0[s]."
ALOG: Warning: The source is compiled without the -dbg switch. Line breakpoints and assertion debug will not be available.
done
# Aldec, Inc. Riviera-PRO version 2017.02.99.6498 built for Linux64 on March 29, 2017.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2017 Aldec, Inc. All rights reserved.
vsim +access+r;
# ELBREAD: Elaboration process.
# ELBREAD: Elaboration time 0.0 [s].
# KERNEL: Main thread initiated.
# KERNEL: Kernel process initialization phase.
# KERNEL: Time resolution set to 1ns.
# ELAB2: Elaboration final pass...
# ELAB2: Create instances ...
# ELAB2: Create instances complete.
# SLP: Started
# SLP: Elaboration phase ...
# SLP: Elaboration phase ... done : 0.0 [s]
# SLP: Generation phase ...
# SLP: Generation phase ... done : 0.0 [s]
# SLP: Finished : 0.1 [s]
# SLP: 0 primitives and 1 (100.00%) other processes in SLP
# SLP: 10 (100.00%) signals in SLP and 0 interface signals
# ELAB2: Elaboration final pass complete - time: 0.1 [s].
# KERNEL: SLP loading done - time: 0.0 [s].
# KERNEL: Warning: You are using the Riviera-PRO EDU Edition. The performance of simulation is reduced.
# KERNEL: Warning: Contact Aldec for available upgrade options - sales@aldec.com.
# KERNEL: SLP simulation initialization done - time: 0.0 [s].
# KERNEL: Kernel process initialization done.
# Allocation: Simulator allocated 5699 kB (elbread=1450 elab2=4114 kernel=134 sdf=0)
# KERNEL: ASDB file was created in location /home/runner/dataset.asdb
run -all;
# KERNEL: -----------------------------------------------------------------
# KERNEL: 0 Process-1 of fork-1 Started
# KERNEL: 0 Process-2 of fork-1 Started
# KERNEL: 0 Process-1 of fork-2 Started
# KERNEL: 0 Process-2 of fork-2 Started
# KERNEL: 5 Process-1 of fork-1 Finished
# KERNEL: 10 Process-1 of fork-2 Finished
# KERNEL: 20 Process-2 of fork-1 Finished
# KERNEL: 22 After disable-fork
# KERNEL: Simulation has finished. There are no more test vectors to simulate.
exit
# VSIM: Simulation has finished.
Done
My opinion is VCS and Aldec is perfect , As per the SV spec , when process is killed all the sub child process should be killed inside the main process, It ain’t happening in the IES tool.
QUERY: What is your answer on this piece of code? Which is preferably tool? What is wrong with these tool results?