Overriding Class properties

SystemVerilog
, , ,
1

Hi All,
Consider the following code ::

class base;
  int a = 10;
  
  virtual function void A();
    $display("a is %0d",a);
  endfunction  
  
endclass

class ext extends base;
  int a = 20;
 
`ifdef OVER                   
  virtual function void A();  // Explicitly override the virtual function
    $display("a is %0d",a);
  endfunction  
`endif
  
endclass

module tb;
  
  base   base_h ;
  ext    ext_h ; 
  
  initial  begin
    ext_h  = new();
    base_h = ext_h;    
    base_h.A();   
  end  

endmodule

My understanding is that objects of class ext have 2 properties named ‘a’
(1) In absence of +define+OVER i.e user doesn’t override the virtual function
I observe o/p as :: a is 10

(2) In presence of +define+OVER i.e user does override the virtual function
I observe o/p as :: a is 20

I am not a 100% clear on the reason behind the observed output and would like to hear from forum

(Q1) For (a) wouldn’t class ext inherit the virtual function by default ?
If yes, then what’s the difference b/w (a) & (b) ?

(Q2) Does scope visibility of property ‘a’ play any part in the output ?

2

By (a) and (b), I think you meant (1) and (2).

Even though class ext inherits the function base::A(), it is still defined in the base class. All references to identifiers are with respect to the base class.