Output of the snippet changes with $display

SystemVerilog
,
1

The program gave output a=1 and b=4 and a 5 ,b 0 without “display” statement in always block , when I include I get the values present in always block. Can anyone explain the reason for this shift in output?

module rr;

  int a;

  int b;

  initial 

    begin 

      a=1;

      b=4;

   end 

  
  always@(*)

    begin 

      

      a=3;

     // $display("%d",a);

      b=7;

    

    end

  initial 
    begin 

      #2;

      a=5;

      b=0;

    end

  initial 

    begin 

      $monitor("%d and %d",a,b);

    end

endmodule
2

In reply to Sv-hustler:

Please use code tags to make your code easier to read. I have added them for you.

The reason is that when you add the $display, the variable a now appears somewhere other than just the LHS of an assignment, so it becomes sensitive to changes on it.

BTW, It’s strongly recommended that you use always_comb instead of always @(*), mainly because it’s guaranteed to execute at least once at time 0.