Output corruption with SVA

SystemVerilog
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4

In reply to muhammadsalmanafzal:

((flush =='b1) ##1 (uop_r=='b0))
From my understanding, it states that “On the current clock cycle(take 30), check for flush==1, if it is true, then on the next clock cycle(40), check for uop_r==0. If uop_r==0 is true, then at 40, assertion should pass.”

Not quite true, but partially. It also states that "“On the current clock cycle(take 30), if flush==0 then the assertion fails. DON’T even bother to check the rest of the sequence”. What you need is vacuity, and this is where the implication operators }-> and |=> come in.
flush =='b1 |=> uop_r=='b0) says
On the current clock cycle(take 30), check for flush==1, if it is true, then on the next clock cycle(40), check for uop_r==0. If uop_r==0 is true, then at 40, assertion should pass. However, if the antecedent is a NO MATCH (i.e., the sequence flush==0) then the property is vacuous. From my book, in the Definition section:

vacuity: (see 3.1, 3.9) A property is vacuous if it lacks serious purpose. Vacuity rules are usually applied when implication operator is used. A property succeeds vacuously if the antecedent is FALSE. A property succeeds non-vacuously only if the consequent of the implication contributes to its success. Many applications have a triggering event that causes the thread to start (in the antecedent), and if the triggering event does not occur (i.e., if false), then there is no need to further evaluate the thread (i.e., the rest of the property for that cycle), which is then considered vacuously true. Also see Success and vacuity and Fail and vacuity. .

… between 50 and 130 is missing,

It is vacuous at this times.

You need to study SVA, you are missing a lot of concepts.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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