In reply to ben@SystemVerilog.us:
Thanks for your reply and sorry for my late reply. I get what you are trying to do, but it still does not explain my query about time 50 and 110. Also, with you code, I get the following output:
# AP | [ 30] | uop_i=3 | flush=1 | stall=1 | uop_r=0 | $past(uop_i)=4
# AP | [ 50] | uop_i=5 | flush=1 | stall=1 | uop_r=0 | $past(uop_i)=3
# AP | [ 130] | uop_i=5 | flush=1 | stall=0 | uop_r=0 | $past(uop_i)=6
# AP | [ 150] | uop_i=f | flush=1 | stall=0 | uop_r=0 | $past(uop_i)=5
# AP | [ 190] | uop_i=d | flush=1 | stall=1 | uop_r=0 | $past(uop_i)=8
Still here, time between 50 and 130 is missing, then there is a cycle miss between 150 and 190 (assuming cycle of 20).
Also, what is wrong with
((flush =='b1) ##1 (uop_r=='b0))
. From my understanding, it states that “On the current clock cycle(take 30), check for flush==1, if it is true, then on the next clock cycle(40), check for uop_r==0. If uop_r==0 is true, then at 40, assertion should pass.”
Am I missing something in regards to sampled value, and updated value due to which I’m not getting correct assertion results?