Nested wait statements

SystemVerilog
,
1

I have written a monitor code, to monitor write/read.

.
.
task run_phase(uvm_phase..);
forever begin
collect_data();
end
.
.
.

task collect_data();

wait(sel==1 && write_state==2'h10);
  begin
     wait(write==1);
       begin
        @(negedge clk);
          pkt.data=inf.data;
          $display("write operation success");
       end
  end
endtask

Is it valid to write a logical AND expression inside wait?
Even though my first 2 wait conditions are false… the $display statement gets printed. Why is that happening?

2

In reply to Curious_cat:

The task you wrote is equivalent to

task collect_data();
  wait(sel==1 && write_state==2'h10). // 1
  wait(write==1)                      // 2
  @(negedge clk)                      // 3
  pkt.data=inf.data;
  $display("write operation success");
endtask

The three timing controls are in series and must succeed in the order they appear. If you want the expressions in controls 1 and 2 to be evaluated when there is a negedge of clk, you can write

task collect_data();
  @(negedge clk iff (sel==1 && write_state==2'h10 && write==1) )  
  pkt.data=inf.data;
  $display("write operation success");
endtask
3

In reply to dave_59:

Thanks you for the reply.
It works :)