Nested wait statements

SystemVerilog
,
2

In reply to Curious_cat:

The task you wrote is equivalent to

task collect_data();
  wait(sel==1 && write_state==2'h10). // 1
  wait(write==1)                      // 2
  @(negedge clk)                      // 3
  pkt.data=inf.data;
  $display("write operation success");
endtask

The three timing controls are in series and must succeed in the order they appear. If you want the expressions in controls 1 and 2 to be evaluated when there is a negedge of clk, you can write

task collect_data();
  @(negedge clk iff (sel==1 && write_state==2'h10 && write==1) )  
  pkt.data=inf.data;
  $display("write operation success");
endtask