Negative number constraints SV

SystemVerilog
,
1

I want to constraint variable a such that it has one bit set high (one hot ) and it should be negative number meaning -1, -2 … -1024 with min and max set as -1 and -1024

shortint a;

constraint c1 {
                  a inside [[-1: -1024]} -> $countones(a) ==1;

}

Above code is incorrect i feel

2

In reply to tejasakulu:

Not only is your code incorrect but your constraints cannot be satisfied. There is only one negative shortint number with only one bit set—16’sh8000, or -32767.

3

In reply to dave_59:

Can you please tell me what is wrong in here if i have to generate negative numbers with just one bit set

4

In reply to tejasakulu:

Can you give us an example of a negative number you would like to see generated with only one bit set? I can only think of one: -32767.

Maybe you mean a negative number with the sign bit set and one other bit set. That would be 2 bits set. Neither -1 nor -1024 meet those constraints.

Or maybe you mean a negative number whose absolute value has only one bit set. Then both -1 and -1024 meet those constraints.

5

In reply to dave_59:
A negative number with the sign bit set and one other bit set. That would be 2 bits set.
Yes you are correct example of negative number FFF0 is -16

6

In reply to tejasakulu:

Then that would simply be $countones(a) == 2, not equal ==1.

rand shortint a;
 
constraint c1 {
                  a inside {[-1024:-1]} && $countones(a) ==2;
 
}

-16 has 12 bits set.

7

In reply to dave_59:

Above constraint has error of conflicting constraints

8

In reply to tejasakulu:

Oh, you can’t use a shortint and restrict the range.

class A;
  
  rand bit signed [10:0] a;
  constraint c1 {
    a inside {[-1024:-1]} && $countones(a) == 2;
  }
endclass

module top;
  
  A h=new;
  
  initial repeat (10) begin
    assert(h.randomize());
    $display("%h %d",h.a,h.a,);
  end
endmodule