In reply to ben@SystemVerilog.us:
Is it possible to use a variable along with $past construct ?
property sig_high_check;
int high_value;
@(posedge clk)
($rose(signal_b), high_value = signal_a_reg) |-> $past($rose(signal_a),high_value);
endproperty
Throws error - variable can’t use along with $past.