Multiple UVM info at same posed cause false increment as a result of which the assertion fails

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

  1. if I use automatic it creates separate thread and increment only once the value remains 1 for all incrementation.

  2. The begin and end is used for `uvm_info or else it shows error.
    4.yes, that it what I meant.

  3. No the logic is working fine, the incrementation also occur as desired except for the few cases in which someone the function gets called twice and which increments the count more than required.
    6.yes, take care of that

Are throughout and until functionally the same? How will be the implementation with throughout?