Multiple UVM info at same posed cause false increment as a result of which the assertion fails

SystemVerilog
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2

In reply to Nimisha Varadkar:
It is difficult for me to debug this unless I get the total picture, such a an assertion testbench. In any case, I do have some pointers and things I noticed about your style.

  1. functions should be automatic, particularly for assertions
  2. Functions should not have side effects, unless they affect the testbench environment, such as support logic.
  3. Overuse of unnecessary begin … end. DO this instead
function automatic int wr_num_exp_instr(int calc_vld_count);
wr_num_exp_instr = calc_vld_count;
`uvm_info("PROPERTY",$psprintf(" EXPECTED INSTRUCTION COUNT :%0d",wr_num_exp_instr) ,UVM_NONE)
endfunction
  1. I fail to understand the wr_act_instr_cnt_func++;
    You mean else wr_act_instr_cnt_func= wr_act_instr_cnt+1’b1; ??
function automatic int wr_act_instr_cnt_func( int wr_exp_instr_cnt);
if(instr_done ==1 || clr == 1) wr_act_instr_cnt_func = 0;
else wr_act_instr_cnt_func++;  // <<< ??? WHAT IS THIS???
`uvm_info("PROPERTY",$psprintf("label ACTUAL VALID COUNT IS :%0d label EXPECTED INSTRUCTION COUNT:%0d ",
wr_act_instr_cnt_func,wr_exp_instr_cnt) ,UVM_NONE)
endfunction
// *** A better way ??
function automatic int wr_act_instr_cnt_func( int wr_exp_instr_cnt, wr_act_instr_cnt);
if(instr_done ==1 || clr == 1) wr_act_instr_cnt_func = 0;
else wr_act_instr_cnt_func= wr_act_instr_cnt+1'b1;  // <<< <------------
`uvm_info("PROPERTY",$psprintf("label ACTUAL VALID COUNT IS :%0d label EXPECTED INSTRUCTION COUNT:%0d ",
wr_act_instr_cnt_func,wr_exp_instr_cnt) ,UVM_NONE)
endfunction
  1. I don’t care for the use of multiple implication operators. DO you really mean vacuity in the 2nd antecendent?
(((enable==1) ##0 first_match( ##[0:$] drm_wr_vld) |->
(((wr_vld, wr_exp_instr_cnt = wr_num_exp_instr(vld_count),
wr_act_instr_cnt = wr_act_instr_cnt_func( wr_exp_instr_cnt)) |->
(wr_act_instr_cnt<=wr_exp_instr_cnt)) until (instr_done,wr_act_instr_cnt =wr_act_instr_cnt_func(wr_exp_instr_cnt))) ;

I understand that the until operator is for a property, and that is why you use the |->. However, you can have a sequence followed by a property with the #-# operator. If you want to stick to sequences, you can use the throughout operator. Thus,

// use this instead
property wr_num_instr_match_num_vld_start_p;
int wr_exp_instr_cnt;
int wr_act_instr_cnt ;
@(posedge clk) disable iff(!rstn || disable_check == 1)
(((enable==1) ##0 first_match( ##[0:$] drm_wr_vld) |->
(((wr_vld, wr_exp_instr_cnt = wr_num_exp_instr(vld_count),
wr_act_instr_cnt = wr_act_instr_cnt_func( wr_exp_instr_cnt, wr_act_instr_cnt)) #-#
(wr_act_instr_cnt<=wr_exp_instr_cnt)) until
(instr_done,wr_act_instr_cnt =wr_act_instr_cnt_func(wr_exp_instr_cnt, wr_act_instr_cnt))) ;
  1. Again, those are general comments. In any case, the assertion should be passive, and can only make changes to the testbench environment, the support logic.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

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