Multiple arguments to foreach loop

SystemVerilog
,
4

In reply to DhavalP:
BTW, Please use code tags making your code easier to read. I have added them for you.

You are getting the proper output for the constraints you wrote. It’s just that you didn’t write the proper constraint for the output you intended to see. :smiling_face:︎

Read this and try:

constraint x_y_width { foreach(x[i]) int’(x[i] + y[i]) < width;
                       width<15; }