Multiple arguments to foreach loop

SystemVerilog
,
3

In reply to dave_59:

Hi Dave,

It is not giving proper output. I have tried as below. I have also constraint width to small value for easy calculation.

Code::

class packet;
 rand bit [7:0] x[10];
 rand bit [7:0] y[10];
 rand bit [7:0] width;

  constraint x_y_width { foreach(x[i]) {x[i] + y[i] < width};                                  width<15;}

endclass

module packet_m;
  packet pkt;
  initial begin
    pkt=new();
    pkt.randomize();
    $display("x=%0p,y=%0p,pkt.width=%0d",pkt.x,pkt.y,pkt.width);
  end
  
endmodule

Output::

x='{'h8c, 'h28, 'ha, 'haa, 'h35, 'h6f, 'h5c, 'h10, 'h94, 'hbf} ,y='{'h7d, 'he2, 'hf6, 'h5f, 'hce, 'h95, 'hac, 'hf5, 'h71, 'h4c} ,pkt.width=13