In reply to ak_verifsj:
I don’t think your implementation is correct.
There is no write_drv/write_rcv method located in uvm_analysis_port #(int) m_ap.
Maybe you wanted to created two diffrent analysis ports for drv and rcv. Each analysis port will be connected to diffrent imp port. You can refer the following code:
////////my_monitor.sv/////////
uvm_analysis_port #(int) m_ap_drv;
uvm_analysis_port #(int) m_ap_rcv;
.....
task write_drv();
@(posedge vif.cb.push)
m_ap_drv.write(vif.cb.data_in);
endtask
task write_rcv();
@(posedge vif.sb.pull)
m_ap_rcv.write(vif.cb.data_out);
endtask
//////////my_scoreboard.sv///////
`uvm_analysis_imp_decl( _drv )
`uvm_analysis_imp_decl( _rcv )
uvm_analysis_imp_drv #(int, my_scoreboard) sb_ap_drv;
uvm_analysis_imp_rcv #(int, my_scoreboard) sb_ap_rcv;
uvm_tlm_fifo #(int) expfifo;
uvm_tlm_fifo #(int) outputfifo;
function void write_drv(int data_in);
expfifo.try_put(data_in);
endfunction
function void write_rcv(int data_out);
outputfifo.try_put(data_out);
endfunction
///////my_en.sv///////
my_agent.my_mon.m_ap_drv.connect(scoreboard.sb_ap_drv);
my_agent.my_mon.m_ap_rcv.connect(scoreboard.sb_ap_rcv);
Also, dont forget to construct the ports.