Monitor for interleaved data

UVM
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1

Hi All,

Can anyone suggest the best way to capture interleaved data in uvm monitor?

Scenario:

2 bit signal (channel): having channel numbers 0,1,1,2,0,0,0,0,2,2,1,1,2,1,1,0,2,1,0,1
1 bit signal (start) : assert high for 20 clock cycle and then assert low.
8 bit signal (data) : random data on every clock cycle.

Need monitor to capture this interleaved data.

Thanks.

2

In reply to KMarshall:

Not really clear what the monitor needs to write out as a transaction. Perhaps you can give some example scenarios

3

In reply to dave_59:

In reply to KMarshall:
Not really clear what the monitor needs to write out as a transaction. Perhaps you can give some example scenarios

Scenario:

  • Every clock (channel number) is changing (0/1/2).
  • Corresponding to each channel, data is there.
  • The moment 1-Bit signal (start) assert,
    data corresponding to each channel should start getting filled in an (analysis port) and should stop on de-assertion of (start) signal.

Please let me know, if still information needed. Else let me know the option to update waveform picture.

4

In reply to KMarshall:

What data structure/transaction do you want the monitor to send out it’s analysis port and when should it do that? It would help to show that in terms of a class definition.

5

In reply to dave_59:

In reply to KMarshall:
What data structure/transaction do you want the monitor to send out it’s analysis port and when should it do that? It would help to show that in terms of a class definition.

bit [31:0] channel_data [channel_number][$];

Data will be pushed to each queue depending on channel number, from assertion of “START” signal, till de-assertion.

Is it the right approach?