Modelsim 10.6: Deferred Immediate Assertion

SystemVerilog
1

Hi all,

How can I enable the tool to recognize deferred immediate assertions? It seems to ignore #0 and print errors when state is not stable yet.

   assert_checkout_0: assert #0 (state == 2'b00  && out == 1'b1) $info  ("state 00/10 has a good out value."); 
        else $error  ("state 00/10 has bad out value.");

Thank you,
Michael

2

Use the assert final instead o the assert #0/ Thus

assert_checkout_0: assert final (state == 2'b00 && out == 1'b1) $info ("state 00/10 has a good out value."); 
else $error ("state 00/10 has bad out value.");

(From my SVA book} to prevent race conditions between the assertion and the value being tested, IEEE 1800 introduced the concept of deferred assertions, which are a kind of immediate assertion. They can be used to suppress false reports that occur due to glitching activities on combinational inputs. Since deferred assertions are a subset of immediate assertions, the term deferred assertion (often used for brevity) is equivalent to the term deferred immediate assertion. The term simple immediate assertion refers to an immediate assertion that is not deferred.

A deferred assertion is similar to a simple immediate assertion, but with the following key differences:
 Syntax: Deferred assertions use #0 (for an Observed deferred assertion) or final (for a final deferred assertion in the Postponed region) after the verification directive.
 Deferral: Reporting is delayed rather than being reported immediately.
 Action block limitations: Action blocks may only contain a single subroutine call.
 Use outside procedures: A deferred assertion may be used as a module_common_item.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
3

In reply to ben@SystemVerilog.us:

Thank you for your suggestion and explanation. Unfortunately, I get an syntax error for using final. It does not seem to work for ModelSim. Michael

 Model Technology ModelSim DE vlog 10.2c Compiler 2013.07 Jul 18 2013
# -- Compiling module one_hot
# ** Error: one_hot.sv(42): near "final": syntax error, unexpected "final".
# ** Error: C:/modelsim_dlx_10.2c/win32pe/vlog failed.
# Error in macro ./run.do line 7
# C:/modelsim_dlx_10.2c/win32pe/vlog failed.
#     while executing
# "vlog -sv one_hot.sv"

     assert_checkout_0: assert **final** (state == 2'b00  && out == 1'b1) $info  ("state 00/10 has a good out value."); 
            else $error  ("state 00/10 has bad out value.");
4

In reply to mikelisfbay:

You need at least Questa 10.3 as this was a new feature of IEEE 1800-2012

5

In reply to dave_59:

I see. Thank you.

Michael