Modelsim 10.6: Deferred Immediate Assertion

SystemVerilog
3

In reply to ben@SystemVerilog.us:

Thank you for your suggestion and explanation. Unfortunately, I get an syntax error for using final. It does not seem to work for ModelSim. Michael

 Model Technology ModelSim DE vlog 10.2c Compiler 2013.07 Jul 18 2013
# -- Compiling module one_hot
# ** Error: one_hot.sv(42): near "final": syntax error, unexpected "final".
# ** Error: C:/modelsim_dlx_10.2c/win32pe/vlog failed.
# Error in macro ./run.do line 7
# C:/modelsim_dlx_10.2c/win32pe/vlog failed.
#     while executing
# "vlog -sv one_hot.sv"

     assert_checkout_0: assert **final** (state == 2'b00  && out == 1'b1) $info  ("state 00/10 has a good out value."); 
            else $error  ("state 00/10 has bad out value.");