Any help possible around the error in Error
Just wondering whether it is because EDA Playground does not support full Modelsim/Questasim
The error message tells you what is wrong:
** Error: (vsim-3978) env.svh(18): Illegal assignment to class work.uvm_pkg::uvm_port_base #(class work.uvm_pkg::uvm_tlm_if_base #(shortint, shortint)) from class work.uvm_pkg::uvm_analysis_imp #(int, class work.uvm_pkg::uvm_subscriber #(int))
You have one port parameterized with ‘int’ and the other parameterized with ‘shortint’. Try using the same datatype for both ports and see if that makes a difference.
In reply to cgales:
Hi,
As per line 18 of your environment, you are connecting the result_monitor_ to scoreboard_h.
But the analysis export declaration is missing in the scoreboard. Try adding the analysis export in the scoreboard
and try running the code.
In reply to sourabhjain08:
The scoreboard extends from uvm_subscriber, which has an implicitly defined analysis_export. That is why he doesn’t need to add another one. However, the type of the analysis export doesn’t match that of the monitor, hence the error.