The error message tells you what is wrong:
** Error: (vsim-3978) env.svh(18): Illegal assignment to class work.uvm_pkg::uvm_port_base #(class work.uvm_pkg::uvm_tlm_if_base #(shortint, shortint)) from class work.uvm_pkg::uvm_analysis_imp #(int, class work.uvm_pkg::uvm_subscriber #(int))
You have one port parameterized with ‘int’ and the other parameterized with ‘shortint’. Try using the same datatype for both ports and see if that makes a difference.