In reply to cgales:
Thank you for your response !
With two different clocks created and passed to interface would be also fine solution as below.
Please give your comments whether for large memory environment this would be right approach.
interface ram_if(input bit a_clk,input bit b_clk);
logic rst;
//logic a_clk;
logic a_wr; // pulse a 1 to write and 0 reads
logic [`RAM_ADDR_WIDTH-1:0] a_addr;
logic [`RAM_DATA_WIDTH-1:0] a_data_in;
logic [`RAM_DATA_WIDTH-1:0] a_data_out;
//logic b_clk;
logic b_wr; // pulse a 1 to write and 0 reads
logic [`RAM_ADDR_WIDTH-1:0] b_addr;
logic [`RAM_DATA_WIDTH-1:0] b_data_in;
logic [`RAM_DATA_WIDTH-1:0] b_data_out;
clocking drv_cb1@(posedge a_clk );
default input #1ns output #1ns;
//all input will be -->output w.r.t TB
output a_wr,a_addr,a_data_in,rst;
input a_data_out;
endclocking
clocking drv_cb2 @(posedge b_clk);
default input #1ns output #1ns;
//all input will be -->output w.r.t TB
output b_wr,b_addr,b_data_in,rst;
input b_data_out;
endclocking
endinterface
Regards
Jayesh J Parmar