How memory allocation is done in system verilog?
In C and all other languages we will learn about memory allocation. So, i wanted to know how system verilog deals with memory allocation.
Section 8.7 of the 2017 LRM contains the text:
SystemVerilog does not require the complex memory allocation and deallocation of C++. Construction of an object is straightforward; and garbage collection, as in Java, is implicit and automatic. There can be no memory leaks or other subtle behaviors, which are so often the bane of C++ programmers.
I’ve always considered this passage more suitable for a book than an Official IEEE Standards Document.
In reply to sbellock:
Agreed. Much of SystemVerilog LRM came from donations from other languages. The term “straightforward” certainly isn’t when put into an IEEE LRM :)
The point is that SystemVerilog has no pointers and does not expose you to any memory allocation details (except allocating elements of dynamically sized arrays)